While investigating utilizing the i.MX 8 for the Librem 5 cellphone we discovered an difficulty that would have been problematic for us to attain the Free of charge Software package Foundation’s “Respects Your Freedom” (RYF) components endorsement:
- In U-Boot there are a amount of firmware blobs that require to be loaded into the DDR PHY so that it can be qualified to work with DDR4. This schooling is finished on each and every boot.
- The usual boot sequence for the i.MX 8 is that the interior ROM loader hundreds the Secondary Program Loader (SPL) which, in this circumstance, is a small model of U-Boot that can initialize the DDR and load the comprehensive U-Boot into DDR to finish the boot system. Pretty early in the SPL, the coaching blobs get loaded into the DDR PHY and the training sequence is run. The DDR teaching treatment is totally un-documented so re-crafting the firmware blobs with absolutely free/libre or open up supply variations would be an arduous process.
- We just cannot overlook the DDR PHY due to the fact it is interface between the i.MX 8 internal buses and the DDR4 chips outside the house of the SOC. The DDR PHY is also part of the i.MX 8 silicon so we just cannot just swap the DDR PHY with a diverse one particular. It also seems that all DDR PHY’s required this schooling to operate with DDR4, so heading to a unique SOC would not clear up it possibly.
The RYF has a “secondary processor” exclusion that can be granted on a circumstance by situation foundation. We will leverage this exclusion to load and teach the DDR PHY on the i.MX 8. We will use a secondary processor to continue to keep binary blobs out of u-boot and the kernel.
- The good news is, the i.MX 8 has some A53 cores and an M4 main all on the similar silicon. The A53 cores operate U-Boot and the Linux kernel and the M4 can operate bare metallic code or a variety of liberated True Time Working Methods (RTOSes). We determined to produce some bare metal M4 code to do the DDR PHY training.
- The M4 has obtain to all of the peripherals connected to the i.MX 8 so our initial proof of principle reads the DDR PHY firmware from the MMC card and then the M4 usually takes around to load it into the DDR PHY. Then U-Boot runs the teaching algorithm and initializes the DDR.
- This is a lot more demanding than it could possibly audio simply because the M4 processor can be booted by U-Boot but it is commonly completed just after the DDR is initialized. The good news is the i.MX 8 also has some on chip RAM that the M4 can use. The U-Boot SPL employs all of the Tightly Coupled Memories (TCM) all through boot so we desired to load the M4 firmware into the On-Chip RAM (OCRAM). There is a simple concept loop in our bare steel code that enables the A53 core to deliver messages to the M4 to load the training firmware into the DDR PHY.
This implementation retains the A53 core “clean” of binary firmware blobs and the M4 is the “secondary processor” that handles the blobs.
We will be modifying this proof of principle for the shipping of the dev package and the Librem 5 cell phone. To more separate the binary blobs from the A53 cores, we will incorporate an SPI flash chip to store the firmware. The SPI flash will be examine only so the firmware blobs can not be modified with no the person knowing.
This technique to the binary blobs has been approved by the FSF beneath the “secondary processor” exception so we are obvious to go ahead with the i.MX 8 processor.
We will go on to keep the FSF up to date on our development, share our components for screening, and progress towards the substantial-bar target of owning the Librem 5 attain the gold-conventional of the No cost Software package Foundation’s Respects Your Freedom endorsement.